When NVIDIA CEO Jensen Huang took the stage at GTC 2026 in San Jose on 16 March, the headline was a platform, not a chip. Vera Rubin bundles seven new pieces of silicon into a single rack-scale system, and NVIDIA said all seven were already in full production.
That framing matters. For most of the past decade the AI hardware story was "which GPU". Vera Rubin is NVIDIA's argument that the GPU is now one component of an "AI factory", and that the network, the CPU and the memory around it are just as decisive.
Key takeaways:
- Announced 16 March 2026 at GTC (16–19 March, SAP Center, San Jose; 30,000+ attendees).
- Seven chips in production: Vera CPU, Rubin GPU, NVLink 6 Switch, ConnectX-9 SuperNIC, BlueField-4 DPU, Spectrum-6 Ethernet switch and the Groq 3 LPU, integrated after NVIDIA's December 2025 licensing deal with Groq.
- Per NVIDIA's keynote figures, the VR200 system delivers about 50 PFLOPS of FP4 compute with 288 GB of HBM4 and roughly 22 TB/s of memory bandwidth.
- The Rubin GPU is built on a 3 nm process with about 336 billion transistors.
- Huang raised NVIDIA's sales projection to $1 trillion through 2027, up from $500 billion through 2026.
- Thinking Machines Lab, founded by former OpenAI CTO Mira Murati, signed a multi-year deal to deploy at least one gigawatt of Vera Rubin systems.
The seven pieces
| Component | Role in the system |
|---|---|
| Vera CPU | General-purpose compute and orchestration |
| Rubin GPU | The main AI accelerator (training and inference) |
| NVLink 6 Switch | Ultra-fast GPU-to-GPU interconnect inside the rack |
| ConnectX-9 SuperNIC | High-speed network interface between racks |
| BlueField-4 DPU | Offloads networking, storage and security work from the CPU |
| Spectrum-6 Ethernet switch | Data-centre-scale Ethernet networking |
| Groq 3 LPU | Dedicated low-latency inference processor, based on technology licensed from Groq |
The inclusion of an LPU is the most interesting design decision. NVIDIA paid roughly $20 billion in December 2025 for a non-exclusive licence to Groq's inference architecture and hired several of its senior engineers. Three months later the result was on stage: the Groq 3 LPU ships in NVIDIA's rack-scale LPX system for inference workloads.
The numbers, and what they mean
| Spec (VR200 vs previous generation) | Vera Rubin VR200 | Blackwell B300 |
|---|---|---|
| FP4 compute | ~50 PFLOPS | — |
| HBM memory | 288 GB HBM4 | — |
| Memory bandwidth | ~22 TB/s | ~8 TB/s |
| Relative throughput | ~3.3× | 1× |
All figures are NVIDIA's own keynote and datasheet claims.
Three terms are worth decoding:
- FP4 is a 4-bit floating-point number format. Using fewer bits per number lets a chip do far more operations per second, at some cost in precision. Modern inference tolerates that trade-off well, which is why FP4 figures are now the headline metric.
- HBM4 is the fourth generation of High Bandwidth Memory, stacked directly beside the GPU. For large models, memory bandwidth, not raw compute, is usually the bottleneck; the jump from about 8 TB/s to about 22 TB/s is the number that matters most.
- NVLink is NVIDIA's proprietary interconnect. At rack scale it lets dozens of GPUs behave more like one enormous processor.
The business claim
Huang also raised NVIDIA's projected sales to $1 trillion through 2027. That is forward guidance, not a result. It is worth quoting only because it signals how large NVIDIA believes the inference market is becoming.
"The inflection point of inference has arrived."
— Jensen Huang, GTC 2026 keynote, 16 March 2026
Concept to take away: training versus inference. Training builds a model; it is a huge one-off job. Inference runs the model every time someone uses it; it is a smaller job repeated billions of times. As AI moves from research into products, inference volume explodes, and the hardware that wins is the hardware that serves tokens cheaply, quickly and at scale. Vera Rubin's LPU, its FP4 focus and its memory bandwidth are all inference decisions.
Why learners should care
If you want to understand modern AI infrastructure, this is the reference architecture everyone else is responding to. Learn the component roles, learn why memory bandwidth outranks FLOPS for large models, and you will be able to read any accelerator announcement critically.
